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General Information
Editor-in-chief

Prof. Pascal Lorenz
University of Haute Alsace, France
 
It is my honor to be the editor-in-chief of IJFCC. The journal publishes good papers in the field of future computer and communication. Hopefully, IJFCC will become a recognized journal among the readers in the filed of future computer and communication.

IJFCC 2012 Vol.1(2): 121-123 ISSN: 2010-3751
DOI: 10.7763/IJFCC.2012.V1.31

Vulnerability Evaluation Method Considering Power Supply Environment for Power Analysis Attacks

Masaya Yoshikawa and Toshiya Asai

Abstract—At present, encryption hardware handling confidential information of integrated circuit (IC) cards or the similar are widely available. Confidential information is protected by encryption algorithms, and its safety is computationally secured. However, the problem of power analysis attacks has been actualized. Power analysis attacks acquire confidential information based on information of power consumption leaked from cryptographic circuits that are embedded in hardware. Therefore, when designing cryptographic circuits, resistance against side-channel attacks must be evaluated. The present study proposes a method to verify the resistance including power supply environment. The present study also verifies the validity of the proposed method through several evaluation experiments.

Index Terms—Vulnerability evaluation, Power analysis attack, Cryptographic circuit, Hardware security

The authors are with Meijo university, Japan (e-mail: dpa_cpa@yahoo.co.jp).

[PDF]

Cite: Masaya Yoshikawa and Toshiya Asai, "Vulnerability Evaluation Method Considering Power Supply Environment for Power Analysis Attacks," International Journal of Future Computer and Communication vol. 1, no. 2, pp. 121-123, 2012.

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