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General Information
    • ISSN: 2010-3751
    • Frequency: Bimonthly (2012-2016); Quarterly (Since 2017)
    • DOI: 10.18178/IJFCC
    • Editor-in-Chief: Prof. Mohamed Othman
    • Executive Editor: Ms. Nancy Y. Liu
    • Abstracting/ Indexing: Google Scholar, Engineering & Technology Digital Library, and Crossref, DOAJ, Electronic Journals LibraryEI (INSPEC, IET).
    • E-mail:  ijfcc@ejournal.net 
Editor-in-chief
Prof. Mohamed Othman
Department of Communication Technology and Network Universiti Putra Malaysia, Malaysia
It is my honor to be the editor-in-chief of IJFCC. The journal publishes good papers in the field of future computer and communication. Hopefully, IJFCC will become a recognized journal among the readers in the filed of future computer and communication.
IJFCC 2013 Vol.2(5):461-465 ISSN: 2010-3751
DOI: 10.7763/IJFCC.2013.V2.206

Clock Gating Aware Low Power ALU Design and Implementation on FPGA

Bishwajeet Pandey and Manisha Pattanaik
Abstract—This paper deals with the design and implementation of a Clock Gating Aware Low Power Arithmetic and Logic Unit that has been developed as part of low power processor design in the platform Xilinx ISE 14.2 and synthesized on 90nm Spartan-3 FPGA. Clock power contributes 45-60 percent of total dynamic power. Hence, clock power reduction is necessary in low power design. In this paper, we analyze theoretical 93.75% clock power reduction in ALU using clock gating techniques. On simulator, we achieved 88.23% clock power reduction using latch based clock gating and 70.58% clock power reduction using latch free clock gating.

Index Terms—Clock gate, ALU, FPGA, LUT, clock power, register transfer level, dynamic power, leakage power

The authors are with the Indian Institute of Information Technology, Gwalior and Centre for Development of Advanced Computing (CDAC), Noida, India (e-mail: gyancity@gyancity.com, manishapattanaik@iiitm.ac.in).

[PDF]

Cite: Bishwajeet Pandey and Manisha Pattanaik, "Clock Gating Aware Low Power ALU Design and Implementation on FPGA," International Journal of Future Computer and Communication vol. 2, no. 5, pp. 461-465, 2013.

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