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General Information
    • ISSN: 2010-3751
    • Frequency: Bimonthly (2012-2016); Quarterly (Since 2017)
    • DOI: 10.18178/IJFCC
    • Editor-in-Chief: Prof. Mohamed Othman
    • Executive Editor: Ms. Nancy Y. Liu
    • Abstracting/ Indexing: Google Scholar, Engineering & Technology Digital Library, and Crossref, DOAJ, Electronic Journals LibraryEI (INSPEC, IET).
    • E-mail:  ijfcc@ejournal.net 
Editor-in-chief
Prof. Mohamed Othman
Department of Communication Technology and Network Universiti Putra Malaysia, Malaysia
It is my honor to be the editor-in-chief of IJFCC. The journal publishes good papers in the field of future computer and communication. Hopefully, IJFCC will become a recognized journal among the readers in the filed of future computer and communication.
IJFCC 2013 Vol.3(1): 31-35 ISSN: 2010-3751
DOI: 10.7763/IJFCC.2014.V3.262

A Compact and Fast FPGA Based Implementation of Encoding and Decoding Algorithm Using Reed Solomon Codes

Aqib Al Azad and Md Imam Shahed
Abstract—This paper presents a compact and fast Field Programmable Gate Array (FPGA) based implementation technique of Encoding and Decoding Algorithm using Reed Solomon (RS) codes, widely used in numerous applications ranging from wireless and mobile communications units to satellite links for correcting multiple errors especially bursttype errors. The main objective of this paper is to provide the reader with a deep understanding of the theory of RS code and encoding and decoding of the codes to achieve efficient detection and correction of the errors. The paper will cover the properties of RS code, RS Encoding and Decoding algorithm, simulation, synthesis and Verilog HDL based hardware implementation in FPGA device of the proposed RS Encoder and Decoder architecture. The results of fast and compact implementations of RS Encoder and Decoder architecture using Xilinx’s Vertex and Spartan3E FPGA device are presented and analyzed. The design can also be synthesized to other FPGA architectures and is fully flexible & parameterized since block lengths and symbol sizes can be readily adjusted to accommodate a wide range of message sizes.

Index Terms—FPGA, RS, Verilog, HDL.

The authors are with the Department of Electrical Engineering and Computer Science, North South University, Dhaka,Bangladesh. He is now with the Department of Electrical and Electronic Engineering, Brac University, Dhaka, Bangladesh (e-mail:aqibazad@ymail.com)

[PDF]

Cite:Aqib Al Azad and Md Imam Shahed, "A Compact and Fast FPGA Based Implementation of Encoding and Decoding Algorithm Using Reed Solomon Codes," International Journal of Future Computer and Communication vol. 2, no. 6, pp. 31-35, 2014.

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