—The proposed design of HDB3 decoding system
using FPGA implementation offers an efficient and unfailing
decoding at receiving end by sustaining clock data recovery
using Direct Digital Synthesis (DDS). The system captures
E1/T1 HDB3 encoded tertiary level stream at input, converts it
into binary level symbols, FPGA IO reconcilable, and decode
and transforms it into synchronized NRZ output. The receiver
end of FPGA based HDB3 decoding system has never been
implemented using clock data recovery. The resource efficient
implementation and synthesis outcome illustrate that the design
of HDB3 decoder is very simple and fault tolerant and its ASIC
design can easily be surrogate by the proposed idea.
—AMI, clock data recovery, decoder, direct
digital synthesis, E1, FPGA, HDB3, NRZ, T1
Imran Ali is with the Department of Electrical and Electronics
Engineering, University of Engineering and Technology Taxila, Pakistan
(e-mail: Engr.ImranAliMirza@ gmail.com).
Ali Ahmed is with the Department of Electronics and Communication,
Hanyang University, South Korea (e-mail: firstname.lastname@example.org).
Cite:Imran Ali and Ali Ahmed, "An Efficient FPGA Based HDB3 Decoding System Using
Direct Digital Synthesis," International Journal of Future Computer and Communication vol. 2, no. 6, pp. 576-580, 2013.