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General Information
    • ISSN: 2010-3751
    • Frequency: Bimonthly (2012-2016); Quarterly (Since 2017)
    • DOI: 10.18178/IJFCC
    • Editor-in-Chief: Prof. Mohamed Othman
    • Executive Editor: Ms. Nancy Y. Liu
    • Abstracting/ Indexing: Google Scholar, Engineering & Technology Digital Library, and Crossref, DOAJ, Electronic Journals LibraryEI (INSPEC, IET).
    • E-mail:  ijfcc@ejournal.net 
Editor-in-chief
Prof. Mohamed Othman
Department of Communication Technology and Network Universiti Putra Malaysia, Malaysia
It is my honor to be the editor-in-chief of IJFCC. The journal publishes good papers in the field of future computer and communication. Hopefully, IJFCC will become a recognized journal among the readers in the filed of future computer and communication.
IJFCC 2017 Vol.6(2): 37-41 ISSN: 2010-3751
doi: 10.18178/ijfcc.2017.6.2.485

Distributed Packet Processing Architecture with Reconfigurable Hardware Accelerators for 100Gbps Forwarding Performance on Virtualized Edge Router

Satoshi Nishiyama, Hitoshi Kaneko, and Ichiro Kudo
Abstract—To implement virtualized service-edge-router functions on carrier networks using general-purpose servers, it is necessary to improve forwarding performance. The required forwarding performance of a service-edge-router reached more than 100-Gbps in bandwidth on carrier networks.
In this paper, we propose a distributed architecture that involves reconfigurable hardware accelerators with high-level synthesis technology for virtualized service-edge functions to satisfy migration time constraints and improve forwarding performance. The proposed architecture prepares several circuit files for the hardware accelerators according to the utilizations of the network functions in advance and selects a suitable circuit file at the time of migration, instead of generating circuit files for the accelerators every time.
The evaluation of the proposed architecture showed that migration time can be almost the same as the time on configurations without hardware accelerators, and forwarding performance can be on the order of 100-Gbps when a general-purpose server exhibits 10-Gbps forwarding performance.

Index Terms—Virtualized service-edge router, hardware accelerator, field-programmable gate array, network function virtualization.

The authors are with the NTT Network Service Systems Labs, Nippon Telegraph and Telephone Corporation, 3-9-11, Midori-cho Musashino-shi, Tokyo, Japan (e-mail: nishiyama.s@lab.ntt.co.jp, kaneko.hitoshi@lab.ntt.co.jp, kudo.ichiro@lab.ntt.co.jp).

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Cite: Satoshi Nishiyama, Hitoshi Kaneko, and Ichiro Kudo, "Distributed Packet Processing Architecture with Reconfigurable Hardware Accelerators for 100Gbps Forwarding Performance on Virtualized Edge Router," International Journal of Future Computer and Communication vol. 6, no. 2, pp. 37-41, 2017.

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