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General Information
    • ISSN: 2010-3751 (Print)
    • Frequency: Semi-annual
    • DOI: 10.18178/IJFCC
    • Editor-in-Chief: Prof. Pascal Lorenz
    • Executive Editor: Ms. Fanny Fang
    • Abstracting/ Indexing: Crossref, Electronic Journals Library, Google Scholar, EBSCO, etc.
    • E-mail:  editor@ijfcc.org
    • Article Processing Charge: 500 USD
Editor-in-chief

Prof. Pascal Lorenz
University of Haute Alsace, France
 
It is my honor to be the Editor-in-Chief of IJFCC. The journal publishes good papers in the field of future computer and communication. Hopefully, IJFCC will become a recognized journal among the readers in the filed of future computer and communication.

IJFCC 2017 Vol.6(2): 37-41
doi: 10.18178/ijfcc.2017.6.2.485

Distributed Packet Processing Architecture with Reconfigurable Hardware Accelerators for 100Gbps Forwarding Performance on Virtualized Edge Router

Satoshi Nishiyama , Hitoshi Kaneko , Ichiro Kudo

  • NTT Network Service Systems Labs, Nippon Telegraph and Telephone Corporation, 3-9-11, Midori-cho Musashino-shi, Tokyo, Japan

Abstract

To implement virtualized service-edge-routerfunctions on carrier networks using general-purpose servers, itis necessary to improve forwarding performance. The requiredforwarding performance of a service-edge-router reached morethan 100-Gbps in bandwidth on carrier networks.<br>In this paper, we propose a distributed architecture thatinvolves reconfigurable hardware accelerators with high-levelsynthesis technology for virtualized service-edge functions tosatisfy migration time constraints and improve forwardingperformance. The proposed architecture prepares severalcircuit files for the hardware accelerators according to theutilizations of the network functions in advance and selects asuitable circuit file at the time of migration, instead ofgenerating circuit files for the accelerators every time.<br>The evaluation of the proposed architecture showed thatmigration time can be almost the same as the time onconfigurations without hardware accelerators, and forwardingperformance can be on the order of 100-Gbps when ageneral-purpose server exhibits 10-Gbps forwardingperformance.

Keywords

  • Virtualized service-edge router
  • hardwareaccelerator
  • field-programmable gate array
  • network functionvirtualization
485-F022

How to Cite

Copied

Satoshi Nishiyama, Hitoshi Kaneko, and Ichiro Kudo, "Distributed Packet Processing Architecture with Reconfigurable Hardware Accelerators for 100Gbps Forwarding Performance on Virtualized Edge Router," International Journal of Future Computer and Communication, vol. 6, no. 2, pp. 37-41, 2017. https://doi.org/ 10.18178/ijfcc.2017.6.2.485

Copyright & License

Copyright © 2017 by the authors. This is an open access article distributed under the Creative Commons Attribution License which permits unrestricted use, distribution, and reproduction in any medium, provided the original work is properly cited (CC BY 4.0).

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