Abstract—This paper presents a compact and fast Field
Programmable Gate Array (FPGA) based implementation
technique of Encoding and Decoding Algorithm using Reed
Solomon (RS) codes, widely used in numerous applications
ranging from wireless and mobile communications units to
satellite links for correcting multiple errors especially bursttype
errors. The main objective of this paper is to provide the
reader with a deep understanding of the theory of RS code and
encoding and decoding of the codes to achieve efficient
detection and correction of the errors. The paper will cover
the properties of RS code, RS Encoding and Decoding
algorithm, simulation, synthesis and Verilog HDL based
hardware implementation in FPGA device of the proposed RS
Encoder and Decoder architecture. The results of fast and
compact implementations of RS Encoder and Decoder
architecture using Xilinx’s Vertex and Spartan3E FPGA
device are presented and analyzed. The design can also be
synthesized to other FPGA architectures and is fully flexible &
parameterized since block lengths and symbol sizes can be
readily adjusted to accommodate a wide range of message
sizes.
Index Terms—FPGA, RS, Verilog, HDL.
The authors are with the Department of Electrical Engineering and
Computer Science, North South University, Dhaka,Bangladesh. He is now
with the Department of Electrical and Electronic Engineering, Brac
University, Dhaka, Bangladesh (e-mail:aqibazad@ymail.com)
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Cite:Aqib Al Azad and Md Imam Shahed, "A Compact and Fast FPGA Based Implementation of
Encoding and Decoding Algorithm Using Reed Solomon
Codes," International Journal of Future Computer and Communication vol. 2, no. 6, pp. 31-35, 2014.